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MICRF600
902-928MHz ISM Band Transceiver Module
General Description
The MICRF600 is a self-contained frequency shift keying (FSK) transceiver module, intended for use in half-duplex, bidirectional RF links. The multi-channeled FSK transceiver module is intended for UHF radio equipment in compliance with the North American Federal Communications Commission (FCC) part 15.247 and 249. The transmitter consists of a fully programmable PLL frequency synthesizer and power amplifier. The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, dual modulus prescaler, programmable frequency dividers, and a phase-detector. The output power of the power amplifier can be programmed to seven levels. A lock-detect circuit detects when the PLL is in lock. In receive mode, the PLL synthesizer generates the local oscillator (LO) signal. The N, M, and A values that give the LO frequency are stored in the N0, M0, and A0 registers. The receiver is a zero intermediate frequency (IF) type that makes channel filtering possible with low-power, integrated low-pass filters. The receiver consists of a low noise amplifier (LNA) that drives a quadrature mix pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel includes a pre-amplifier, a third order Sallen-Key RC low-pass filter that protects the following switched-capacitor filter from strong adjacent channel signals, and a limiter. The main channel filter is a switched-capacitor implementation of a six-pole elliptic low pass filter. The cut-off frequency of the Sallen-Key RC filter can be programmed to four different frequencies: 100kHz, 150kHz, 230kHz, and 350kHz. The I and Q channel outputs are demodulated and produce a digital data output. The demodulator detects the relative phase of the I and the Q channel signal. If the I channel signal lags behind the Q channel, the FSK tone frequency is above the LO frequency (data "1"). If the I channel leads the Q channel, then the FSK tone is below the LO frequency (data "0"). The output of the receiver is available on the DataIXO pin. A receive signal strength indicator (RSSI) circuit indicates the received signal level. All support documentation can be found on Micrel's web site at: www.micrel.com.
RadioWire(R) Module
Features
* * * * * * * * * * * * "Drop in" RF solution Small size: 11.5x14.1mm RF tested FCC Compliant Low Power Surface Mountable Tape & Reel Digital Bit Synchronizer Received Signal Strength Indicator (RSSI) RX and TX power management Power down function Register read back function
Applications
* * * * * * * Telemetry Remote metering Wireless controller Remote data repeater Remote control systems Wireless modem Wireless security system
RadioWire(R) is a trademark of Micrel, Inc Power, Connect and Protect is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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Contents
General Description ................................................................................................................................................................ 1 Features .................................................................................................................................................................................. 1 Applications ............................................................................................................................................................................. 1 Contents .................................................................................................................................................................................. 2 RadioWire(R) RF Module Selection Guide................................................................................................................................. 3 Ordering Information ............................................................................................................................................................... 3 Block Diagram ......................................................................................................................................................................... 3 Pin Configuration..................................................................................................................................................................... 4 Pin Description ........................................................................................................................................................................ 4 Absolute Maximum Ratings(1) ................................................................................................................................................. 5 Operating Ratings(2) ................................................................................................................................................................ 5 Electrical Characteristics......................................................................................................................................................... 5 Programming........................................................................................................................................................................... 7 General ............................................................................................................................................................................... 7 Writing to the Control Registers in MICRF600 ................................................................................................................... 8 Writing to a Single Register ................................................................................................................................................ 8 Writing to All Registers ....................................................................................................................................................... 8 Writing to n Registers Having Incremental Addresses ....................................................................................................... 9 Reading from the Control Registers in MICRF600 ............................................................................................................. 9 Reading n Registers from MICRF600................................................................................................................................. 9 Programming Interface Timing.............................................................................................................................................. 10 Programming Summary.................................................................................................................................................... 11 Frequency Synthesizer ......................................................................................................................................................... 11 Crystal Oscillator (XCO) ................................................................................................................................................... 11 VCO .................................................................................................................................................................................. 12 Lock Detect ....................................................................................................................................................................... 12 Modes of Operation............................................................................................................................................................... 12 Transceiver Sync/Non-Synchronous Mode ...................................................................................................................... 13 Data Interface ................................................................................................................................................................... 13 Receiver ................................................................................................................................................................................ 13 Front End .......................................................................................................................................................................... 14 Sallen-Key Filters.............................................................................................................................................................. 14 Switched Capacitor Filter.................................................................................................................................................. 14 RSSI.................................................................................................................................................................................. 14 FEE ................................................................................................................................................................................... 15 Bit Synchronizer................................................................................................................................................................ 15 Transmitter ............................................................................................................................................................................ 16 Power Amplifier................................................................................................................................................................. 16 Frequency Modulation ...................................................................................................................................................... 16 Using the XCO-tune Bits ....................................................................................................................................................... 16 Application Circuit Illustration ................................................................................................................................................ 17 Assembling the MICRF600 ................................................................................................................................................... 17 Recommended Reflow Temperature Profile .................................................................................................................... 17 Shock/Vibration during Reflow.......................................................................................................................................... 17 Handassembling the MICRF600....................................................................................................................................... 17 Layout.................................................................................................................................................................................... 18 Recommended Land Pattern............................................................................................................................................ 18 Layout Considerations ...................................................................................................................................................... 18 Package Dimensions ............................................................................................................................................................ 19 Tape Dimensions .................................................................................................................................................................. 19
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RadioWire(R) RF Module Selection Guide
Device MICRF600 MICRF610 MICRF620 RFB433B RFB868B RFB915B Frequency Range 902-928 MHz 868-870 MHz 430-440 MHz 430-440 MHz 868-870 MHz 902-928 MHz Data Rate <20 kbps <15 kbps <20 kbps 19.2 kbaud 19.2 kbaud 19.2 kbaud Receive 13.5 mA 13.5 mA 12.0 mA 8 mA 10 mA 10 mA Supply Voltage 2.0-2.5 v 2.0-2.5 v 2.0-2.5 v 2.5-3.4 V 2.5-3.4 V 2.5-3.4 V Transmit 28 mA 28 mA 24 mA 42 mA 50 mA 50 mA Modulation Type FSK FSK FSK FSK FSK FSK Package 11.5x14.1 mm 11.5x14.1 mm 11.5x14.1 mm 1"x1" 1"x1" 1"x1"
Ordering Information
Part Number MICRF600 TR Junction Temp. Range(1) -20 to +70C Package 11.5 x 14.1mm
Block Diagram
SCLK
IFAMP
Sallen-key
Main filter
Clock recovery Demodulator
IO CS
LNA IFAMP
Sallen-key
Main filter
Control logic
DataIXO DataClk
ANT LO-Buffer DIV 2
RSSI
Deviation control
Modulator
PA-buffer
RSSI
PA
LDout Frequency Synthesiser
XCO
VCO
Bias
MICRF600
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Pin Configuration
16 VDD 15 GND 14 ANT 13 GND 12 GND 11 10
1
2 3 CS 4 5 SCLK IO
6 DataIXO 7 9 8 DataClk
MICRF600 TR 11.5 x 14.1 mm (Top view)
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name NC NC CS SClk IO DataIXO DataClk LD RSSI GND GND GND ANT GND VDD GND I/O I I I/O I/O O O O Type Pin Function Not connected Not connected Chip select, three wire programming interface Clock, three wire programming interface Data, three wire programming interface Data receive/transmit, bi-directional Data clock receive/transmit Lock detect Receive signal strength indicator Ground Ground Ground RF In/Out Ground VDD (2.0-2.5V) Ground
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Absolute Maximum Ratings(1)
Supply Voltage (VDD)...................................................+3.3V Voltage on any pin (GND = 0V). ..................... -0.3V to 2.7V Lead Temperature (soldering, 5 sec.) ......................+225C Storage Temperature (Ts) ............................-30C to +85C ESD Rating(3) ..................................................................2kV
Operating Ratings(2)
Supply voltage (VIN) ..................................+2.0V to +2.5V RF Frequencies................................. 902MHz to 928MHz Data Rate (NRZ) ................................................ <20 kbps Ambient Temperature (TA) .......................-20C to +70C
Electrical Characteristics
fRF = 915MHz, Data rate = 20kbps, VDD = 2.5V; TA = 25C, bold values indicate -20C< TA < +70C, unless noted.
Symbol Parameter Power Supply Power Down Current Standby Current VCO and PLL Section Crystal Oscillator Frequency Crystal Initial Tolerance Crystal Temperature Tolerance Rx 915MHz - Rx 915.5MHz Rx 903MHz - Rx 926MHz Rx - Tx, same frequency Switch Time Tx - Rx, same frequency, time to good data Standby - Rx, Standby - Tx Crystal Oscillator Start-Up Time Transmit Section Output Power Output Power Tolerance Tx Current Consumption Tx Current Consumption Variation Binary FSK Frequency Separation Data Rate(5) Occupied bandwidth 2nd Harmonic 3 Harmonic Spurious Emission < 902 MHz Spurious Emission > 928 MHz
rd (5)
Condition
Min 2.0
Typ 0.3 280
Max 2.5
Units V A A MHz
Tunable with on-chip cap bank Tuning range -30 -10 -10
16 +40 +10 +10 250 850 200 300 1.0 1.0 750 9 -7 2 3 28 14 2.5 20 0 320 -20 400 20
ppm ppm ppm s s s s ms ms s dBm dBm dB dB mA mA mA kHz kbps kHz dBc dBm dBm dBm
XCO_tune=13 RLOAD = 50, Pa2-0-111 RLOAD = 50, Pa2-0-001 Over temperature range Over power supply range RLOAD = 50, PA2_0: 111 RLOAD = 50, PA2_0: 001 RLOAD = 50, PA2_0: 111 Limited by receiver BW NRZ 20kbps, = 10 (100kHz), 20dBc (RBW=10kHz)
FCC part 15, RLOAD = 50
-41.2 -49.2 -41.2
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Symbol
Parameter
Condition All functions on
Min
Typ 13.5 11.5 11.5 4 -111 -110 -109 -107 -104 -10 4 1
Max
Units mA mA mA mA dBm dBm dBm dBm dBm dBm dB dB
Receive Section Rx Current Consumption Rx Current Consumption Variation LNA bypass Switch cap filter bypass with LNA Over temperature 2.4 kbps, = 16, SC=50 kHz 4.8 kbps, = 16, SC=50 kHz Receiver Sensitivity 4.8 kbps, = 4, SC=50 kHz 19.2 kbps, =8, SC=200 kHz 19.2 kbps, =2, SC=67 kHz Receiver Maximum Input Power Receiver Sensitivity Tolerance Receiver Bandwidth Co-Channel Rejection Adjacent Channel Rejection 19.2 kbps, = 8, SC=133 kHz 200 kHz spacing 500 kHz spacing 1 MHz spacing Desired signal: 19.2 kbps, =8, 3dB above sens, SC=133 kHz Offset 1MHz Offset 2MHz Offset 5MHz Offset 10MHz Offset 30MHz 19.2 kbps, = 10 Over temperature Over power supply range 50 -9 TBD TBD TBD 55 58 48 50 60 -35 2 tones with 1MHz separation -25 TBD -90 < 902 MHz > 928 MHz 50 Pin = -100 dBm Pin = -60 dBm 0.7VDD 0
(4)
350
kHz dB
dB dB dB dB dB dB dBm dBm dBm dBm dBm dB V V VDD 0.3VDD 10 55 V V MHz % -49.2 -41.1
Blocking
1dB Compression Input IP3 Input IP2 LO Leakage Spurious Emission Input Impedance(5) RSSI Dynamic Range RSSI Output Range Digital Inputs/Outputs Logic Input High Logic Input Low Clock/Data Frequency(4) Clock/Data Duty Cycle
Notes: 1. 2. 3. 4.
1.2 2.2
45
Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Guaranteed by design.
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Programming
General The MICRF600 functions are enabled through a number of programming bits. The programming bits are organized as a set of addressable control registers, each register holding 8 bits. There are 23 control registers in total in the MICRF600, and they have addresses ranging from 0 to 22. The user can read all the control registers. The user can write to the first 22 registers (0 to 21); the register 22 is a read-only register. All control registers hold 8 bits and all 8 bits must be written to when accessing a control register, or they will be read. Some of the registers do not utilize all 8 bits. The value of an unused bit is "don't care." The control register with address 0 is referred to as ControlRegister0, the control register with address 1 is ControlRegister1 and so on. A summary of the control registers is given in the table below. In addition to the unused bits (marked with"-") there are a number of fixed bits (marked with "0" or "1"). Always maintain these as
Address A6...A0 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 D7 LNA_by `1' `0' `1' `0' D6 PA2 `0' `SC_by' `1' `0' D5 PA1 `0' `0' `0' `0' `0' D4 PA0 `0' `PA_by' VCO_IB2 `0' `1'
shown in the table. The control registers in MICRF600 are accessed through a 3-wire interface; clock, data and chip select. These lines are referred to as SCLK, IO, and CS, respectively. This 3wire interface is dedicated to control register access and is referred to as the control interface. Received data (via RF) and data to transmit (via RF) are handled by the DataIXO and DataClk (if enabled) lines; this is referred to as the data interface. The SCLK line is applied externally; access to the control registers are carried out at a rate determined by the user. The MICRF600 will ignore transitions on the SCLK line if the CS line is inactive. The MICRF600 can be put on a bus, sharing clock and data lines with other devices. All control registers should be written to after a battery reset. During operation, it is sufficient to write to one register only. The MICRF600 will automatically enter power down mode after a battery reset.
Data D3 Sync_en RSSI_en `0' VCO_IB1 `0' D2 Mode1 LD_en `0' VCO_IB0 `0' D1 Mode0 PF_FC1 `0' VCO_freq1 `0' D0 `1' PF_FC0 `0' VCO_freq0 `0'
`0' `0' `0' 0000111 BitRate_clkS1BitRate_clkS0 RefClk_K5 RefClk_K4 `1' `0' N0_7 M0_7 N1_7 M1_7 `1' FEE_7 `1' `1' N0_6 M0_6 N1_6 M1_6 `0' FEE_6 ScClk5 `1' A0_5 N0_5 M0_5 A1_5 N1_5 M1_5 `1' FEE_5 ScClk4 XCOtune4 A0_4 N0_4 M0_4 A1_4 N1_4 M1_4 `1' FEE_4
`0' `0' `0' `0' BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2 RefClk_K3 ScClk3 XCOtune3 A0_3 N0_11 N0_3 M0_11 M0_3 A1_3 N1_11 N1_3 M1_11 M1_3 `0' FEEC_3 FEE_3 RefClk_K2 ScClk2 XCOtune2 A0_2 N0_10 N0_2 M0_10 M0_2 A1_2 N1_10 N1_2 M1_10 M1_2 `1' FEEC_2 FEE_2 RefClk_K1 ScClk1 XCOtune1 A0_1 N0_9 N0_1 M0_9 M0_1 A1_1 N1_9 N1_1 M1_9 M1_1 `0' FEEC_1 FEE_1 RefClk_K0 ScClk0 XCOtune0 A0_0 N0_8 N0_0 M0_8 M0_0 A1_0 N1_8 N1_0 M1_8 M1_0 `1' FEEC_0 FEE_0
Table 1. Control Registers in MICRF600
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Writing to the Control Registers in MICRF600 Writing: A number of octets are entered into MICRF600, followed by a load-signal to activate the new setting. Making these events is referred to as a "write sequence." It is possible to update all, 1, or n control registers in a write sequence. The address to write to (or the first address to write to) can be any valid address (0-21). The IO line is always an input to the MICRF600 (output from user) when writing.
What to write:
Field Address: R/W bit: Values:
Comments 7 bit = A6, A5, ...A0 (A6 = msb. A0 = lsb) "0" for writing 8 bits = D7, D6, ...D0 (D7 = msb, D0 = lsb)
Table 3. "Address" and "R/W bit" together make 1 octet In addition, 1 octet with programming bits is entered. Totally, 2 octets are clocked into the MICRF600. How to write:
* * *
CS
Bring CS high Use SCLK and IO to clock in the 2 octets Bring CS low
*
The address of the control register to write to (or if more than 1 control register should be written to, the address of the 1st control register to write to). A bit to enable reading or writing of the control registers. This bit is called the R/W bit. The values to write into the control register(s).
Comments A 7-bit field, ranging from 0 to 21. MSB is written first. A 1-bit field, = "0" for writing A number of octets (1-22 octets). MSB in every octet is written first. The first octet is written to the control register with the specified address (="Address"). The next octet (if there is one) is written to the control register with address = "Address + 1" and so on.
SCLK IO
* *
Field Address: R/W bit: Values:
A6
A5
A0
RW
D7
D6
D2
D1
D0
Address of register i
RW
Data to write into register i Internal load pulse made here
Figure 1. How to write to a single Control Register
Table 2. Writing to the Control Registers How to write:
In Figure 1, IO is changed at positive edges of SCLK. The MICRF600 samples the IO line at negative edges. The value of the R/W bits is always "0" for writing. Writing to All Registers After a power-on, all writable registers must be written. This is described here: Writing to all register can be done at any time. To get the simplest firmware, always write to all registers. The price to pay for the simplicity is increased write-time, which leads to increased time for changing the way the MICRF600 works. What to write
Field Address: R/W bit: Values: Comments `000000' (address of the first register to write to, which is 0) "0" for writing 1st Octet: wanted values for ControlRegister0. 2nd Octet: wanted values for ControlRegister1 and so on for all of the octets. So the 22nd octet: wanted values for ControlRegister21. Refer to the specific sections of this document for actual values.
Bring CS active to start a write sequence. The active state of the CS line is "high." Use the SCLK/IO serial interface to clock "Address" and "R/W" bit and "Values" into the MICRF600. MICRF600 will sample the IO line at negative edges of SCLK. Make sure to change the state of the IO line before the negative edge. Refer to figures below. Bring CS inactive to make an internal load-signal and complete the write-sequence.
The two different ways to "program the chip" are:
*
Write to a number of control registers (0-22) when the registers have incremental addresses (write to 1, all or n registers) Write to a number of control registers when the registers have non-incremental addresses.
*
Table 4. "Address" and "R/W bit" together make 1 octet
Writing to a Single Register Writing to a control register with address "A6. A5, ...A0" is described here. During operation, writing to 1 register is sufficient to change the way the transceiver works. Typical example: Change from receive mode to power-down.
In total, 23 octets are clocked into the MICRF600.
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How to write:
* * *
Bring CS high Use SCLK and IO to clock in the 23 octets Bring CS low
Refer to the figure in the next section, "Writing to n registers having incremental addresses". Writing to n Registers Having Incremental Addresses In addition to entering all bytes, it is also possible to enter a set of n bytes, starting from address i = "A6, A5, ... A0". Typical example: Clock in a new set of frequency dividers (i.e. change the RF frequency). "Incremental addresses". Registers to be written are located in i, i+1, i+2. What to write:
Field Address: R/W bit: Values: Comments 7 bit = A6, A5, ...A0 (A6 = msb. A0 = lsb) (address of first byte to write to) "0" for writing n* 8 bits = D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i") D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i+1") D7, D6, ...D0 (D7 = msb, D0 = lsb) (written to control reg. with address "i+n-1")
Reading from the Control Registers in MICRF600 The "read-sequence" is: 1. Enter address and R/W bit 2. Change direction of IO line 3. Read out a number of octets and change IO direction back again. It is possible to read all, 1 or n registers. The address to read from (or the first address to read from) can be any valid address (0-22). Reading is not destructive, i.e. values are not changed. The IO line is output from the MICRF600 (input to user) for a part of the read-sequence. Refer to procedure description below. A read-sequence is described for reading n registers, where n is number 1-23. Reading n Registers from MICRF600
CS
SCLK IO A6 A5 A0 RW D7 D6 D0
Address of register i Simple time
RWData read from reg. i
Table 5. "Address" and "R/W bit" together make 1 octet
In addition, n octets with programming bits are entered. Totally. 1 +n octets are clocked into the MICRF600.
How to write:
IO Input IO Output
Figure 3. How to read from many Control Registers
* * *
Bring CS high Use SCLK and IO to clock in the 1 + n octets Bring CS low
In Figure 3, 1 register is read. The address is A6, A5, ... A0. A6 = msb. The data read out is D7, D6, ...D0. The value of the R/W bit is always "1" for reading. SCLK and IO together form a serial interface. SCLK is applied externally for reading as well as for writing. * * * Bring CS active Enter address to read from (or the first address to read from) (7 bits) and The R/W bit = 1 to enable reading Make the IO line an input to the user (set pin in tristate) Read n octets. The first rising edge of SCLK will set the IO as an output from the MICRF600. MICRF will change the IO line at positive edges. The user should read the IO line at the negative edges. Make the IO line an output from the user again.
In Figure 1, IO is changed at positive edges of SCLK. The MICRF600 samples the IO line at negative edges. The value of the R/W bits is always "0" for writing.
CS
SCLK IO A6 A5 A0 RW D7 D6 D2 D1 D0
* *
Address of first register to write to, register i RW Data to write into register i Data to write into register i+1
Internal load pulse made here
Figure 2. How to write to many Control Registers
*
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Programming Interface Timing
Figure 4 and Table 6 show the timing specification for the 3-wire serial programming interface.
Tcsr traise tfall Tper Thigh Tread Tlow Twrite Tscl
SCLK CS
IO
A6
A5
A0
RW
D7
D6
D2
D1
D0
Address Register
Data Register LOAD
Figure 4. Programming Interface Timing
Values Symbol Tper Thigh Tlow tfall trise Tcsr Tcsf Twrite Tread Parameter Min. period of SCLK (Voltage dividers on IO lines will slow down the write/read frequency) Min. high time of SCLK Min. low time of SCLK Max. time of falling edge of SCLK Max. time of rising edge of SCLK Max. time of rising edge of CS to falling edge of SCLK Min. delay from rising edge of CS to rising edge of SCLK Min. delay from valid IO to falling edge of SCLK during a write operation Min. delay from rising edge of SCLK to valid IO during a read operation (assuming load capacitance of IO is 25pF) Time from power up to first rising edge of CS (Assuming Vdd rail rise time of 100 sec) Table 6. Timing Specification for the 3-wire Programming Interface 0 5 0 75 3.4 Min. 50 20 20 1 1 Typ. Max. Units ns ns ns s s ns ns ns ns ms
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Programming Summary * * * * * * * * * * Use CS, SCLK, and IO to get access to the control registers in MICRF600. SCLK is user-controlled. Write to the MICRF600 at positive edges (MICRF600 reads at negative edges). Read from the MICRF600 at negative edges (MICRF600 writes at positive edges) After power-on: Write to the complete set of control registers. Address field is 7 bits long. Enter msb first. R/W bit is 1 bit long ("1" for read, "0" for write) Address and R/W bit together make 1 octet All control registers are 8 bits long. Enter/read msb in every octet first. Always write 8 bits to/read 8 bits from a control register. This is the case for registers with less than 8 used programming bits as well. Writing: Bring CS high, write address and R/W bit followed by the new values to fill into the addressed control register(s) and bring CS low for loading, i.e., activation of the new control register values. Reading: Bring CS high, write address and R/W bit, set IO as an input, read present contents of the addressed control register(s), bring CS low and set IO an output.
Frequency Synthesizer
A6...A0 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 D7 N0_7 M0_7 N1_7 M1_7 D6 N0_6 M0_6 N1_6 M1_6 D5 A0_5 N0_5 M0_5 A1_5 N1_5 M1_5 D4 A0_4 N0_4 M0_4 A1_4 N1_4 M1_4 D3 A0_3 N0_11 N0_3 M0_11 M0_3 A1_3 N1_11 N1_3 M1_11 M1_3 D2 A0_2 N0_10 N0_2 M0_10 M0_2 A1_2 N1_10 N1_2 M1_10 M1_2 D1 A0_1 N0_9 N0_1 M0_9 M0_1 A1_1 N1_9 N1_1 M1_9 M1_1 D0 A0_0 N0_8 N0_0 M0_8 M0_0 A1_0 N1_8 N1_0 M1_8 M1_0
The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, phase select prescaler, programmable frequency dividers and a phasedetector. The length of the N, M, and A registers are 12, 12 and 6 respectively. The N, M, and A values can be calculated from the formula:
f PhD =
f XCO f VCO f RF , = = (31 x N + A ) (31 x N + A )/2 M
1A*
PhD: Phase detector comparison frequency fXCO: Crystal oscillator frequency fVCO: Voltage controlled oscillator frequency fRF: Input/output RF frequency There are two sets of each of the divide factors (i.e. A0 and A1). Storing the `0' and the `1' frequency in the 0- and the 1 registers respectively, does the 2-FSK. The receive frequency must be stored in the `0' registers. Crystal Oscillator (XCO)
Adr 0001001 D7 `0' D6 `1' D5 `1' D4 XCOtune4 D3 XCOtune3 D2 XCOtune2 D1 XCOtune1 D0 XCOtune0
*
The crystal oscillator is a reference for the RF output frequency and the LO frequency in the receiver. It is possible to tune the internal crystal oscillator by switching in internal capacitance using 5 tune bits XCOtune4 - XCOtun0. The benefit of tuning the crystal oscillator is to eliminate the initial tolerance and the tolerance over temperature and aging. By using the crystal tuning feature the noise bandwidth of the receiver can be reduced and a higher sensitivity is achieved. When XCOtune4 - XCOtune0 = 0 no internal capacitors are connected to the crystal pins. When XCOtune4 - XCOtune0 = 1 all of the internal capacitors are connected to the crystal pins. Figure 5 shows the tuning range.
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Tuning range
55.0 45.0 25.0 [ppm] 15.0 5.0 -5.0 -15.0 -25.0 -35.0 -45.0 0 4 8 12 16 20 24 28 32 [XCO_tune value] 35.0
1000 Frequency (MHz) 950 900 850 800 0 0,5 1 1,5 2 2,5 Varactor voltage (V) '10' '11'
Figure 5. XCO Tuning
The typical start up time for the crystal oscillator (default XCO_tune=13) is ~750us. If more capacitance is added (higher XCO_tune value), then the start-up time will be longer. To save current in the crystal oscillator start-up period, the XCO is turned on before any other circuit block. When the XCO has settled, rest of the circuit will be turned on. No programming should be made during this period. The current consumption during the prestart period is approximately 280A. VCO
A6..A0 0000011 D7 `1' D6 `1' D5 `0' D4 VCO_IB2 D3 VCO_IB1 D2 VCO_IB0 D1 VCO_freq1 D0 VCO_freq0
Figure 6. RF Frequency vs. Varactor Voltage and VCO Frequency bit (VDD = 2.25V)
Lock Detect
A6..A0 0000001 D7 `1' D6 `0' D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
A lock detector can be enabled by setting LD_en = 1. When pin LD is high, it indicates that the PLL is in lock. When entering TX, the procedure is first to load the TX word and then turn on the PA stage. During the PA ramp up time, the LD signal may indicate out of lock. It is first when the PA stage is fully on that the LD signal will indicate in "Lock". During transmission, the Lock Detect signal will have transitions and the user should therefore, ignore the Lock detect signal.
The VCO has no external components. It has three bit to set the bias current and two bit to set the VCO frequency. These five bits are set by the RF frequency, as follows:
RF freq. 915MHz 950MHz VCO_IB2 0 0 VCO_IB1 0 0 VCO_IB0 1 0 VCO_freq1 VCO_freq0 1 1 0 1
Modes of Operation
A6..A0 0000000 D7 LNA_by D6 PA2 D5 PA1 D4 PA0 D3 Sync_en D2 Mode1 D1 Mode0 D0 '1'
Mode1 0 0 1 1
Mode0 0 1 0 1
State Power down Standby Receive Transmit
Comments Keeps register configuration Only crystal oscillator running Full receive Full transmit ex PA state
Table 7. VCO Bit Setting
The bias bit will optimize the phase noise, and the frequency bit will control a capacitor bank in the VCO. The tuning range the RF frequency versus varactor voltage is dependent on the VCO frequency setting, and can be shown in Figure 6.
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Transceiver Sync/Non-Synchronous Mode
A6..A0 0000000 0000110 0000111
Sync_en 0 0 1 1
D7 D6 LNA_by PA2 `0' BitRate_clkS1 BitRate_clkS0
State Rx: Bit synchronization off Tx: DataClk pin off Rx: Bit synchronization on Tx: DataClk pin on Comments
D5 PA1 `0' RefClk_K5
D4 D3 D2 D1 D0 PA0 Sync_en Mode1 Mode0 '1' `0' BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
Transparent reception of data Transparent transmission of data Bit-clock is generated by transceiver Bit-clock is generated by transceiver
The data interface is defined in such a way that all user actions should take place on falling edge and is illustrated Figure 7 and 8. The two figures illustrate the relationship between DATACLK and DATAIXO in receive mode and transmit mode. MICRF600 will present data on rising edge and the "USER" sample data on falling edge in receive mode.
DATAIXO
When Sync_en = 1, it will enable the bit synchronizer in receive mode. The bit synchronizer clock needs to be programmed, see chapter Bit synchronizer. The synchronized clock will be set out on pit DataClk. In transmit mode, when Sync_en = 1, the clock signal on pin DataClk is a programmed bit rate clock. Now the transceiver controls the actual data rate. The data to be transmitted will be sampled on rising edge of DataClk. The micro controller can therefore use the negative edge to change the data to be transmitted. The clock used for this purpose, BitRate-clock, is programmed in the same way as the modulator clock and the bit synchronizer clock:
fBITRATE_CL K = where: fBITRATE_CLK: The clock frequency used to control the bit rate, should be equal to the bit rate (bit rate of 20 kbit/sec requires a clock frequency of 20kHz) fXCO: Crystal oscillator frequency Refclk_K: 6 bit divider, values between 1 and 63 BitRate_clkS: Bit rate setting, values between 0 and 6 f XCO Refclk_K x 2 (7-BITRATE_c lkS)
DATACLK
Figure 7. Data Interface in Receive Mode The User presents data on falling edge and MICRF600 samples on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 8. Data Interface in Transmit Mode
Receiver
The receiver is a zero intermediate frequency (IF) type in order to make channel filtering possible with low-power integrated low-pass filters. The receiver consists of a low noise amplifier (LNA) that drives a quadrature mixer pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel includes a pre-amplifier, a third order Sallen-Key RC lowpass filter from strong adjacent channel signals and finally a limiter. The main channel filter is a switched-capacitor implementation of a six-pole elliptic lowpass filter. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the Sallen-Key RC filter can be programmed to four different frequencies: 100kHz, 150kHz, 230kHz and 340kHz. The demodulator demodulates the I and Q channel outputs and produces a digital data output. If detects the relative phase of the I and Q channel signal. If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data `1'). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data `0'). The output of the receiver is available on the DataIXO pin. A RSSI circuit (receive signal strength indicator) indicates the received signal level.
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Data Interface The MICRF600 interface can be divided in to two separate interfaces, a "programming interface" and a "Data interface". The "programming interface" has a three wire serial programmable interface and is described in chapter Programming.
The "data interface" can be programmed to sync-/nonsynchronous mode. In synchronous mode the MICRF600 is defined as "Master" and provides a data clock that allows users to utilize low cost micro controller reference frequency.
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MICRF600
Front End
A6..A0 0000000 D7 LNA_by D6 PA2 D5 PA1 D4 PA0 D3 Sync_en D2 Mode1 D1 Mode0 D0 '1'
fCUT: Filter cutoff frequency fXCO: Crystal oscillator frequency ScCLK: Switched capacitor filter clock, bits ScClk5-0 1 order RC lowpass filters are connected to the output of the SC filter to filter the clock frequency. The lowest cutoff frequency in the pre- and the main channel filter must be set so that the received signal is passed with no attenuation, that is frequency deviation plus modulation. If there are any frequency offset between the transmitter and the receiver, this must also be taken into consideration. A formula for the receiver bandwidth can be summarized as follows:
st
A low noise amplifier in RF receivers is used to boost the incoming signal prior to the frequency conversion process. This is important in order to prevent mixer noise from dominating the overall front-end noise performance. The LNA is a two-stage amplifier and has a nominal gain of approximately 23dB at 900MHz. The front end has a gain of about 33dB to 35dB. The gain varies by 1-1.5dB over a 2.0V to 2.5V variation in power supply. The LNA can be bypassed by setting bit LNA_by to `1'. This can be useful for very strong input signal levels. The front-end gain with the LNA bypassed is about 9-10dB. The mixers have a gain of about 10dB at 900MHz.
fBW = + fOFFSET + fDEV + Baudrate / 2
where fBW: Needed receiver bandwidth, fcut above should not be smaller than fBW (Hz) foffset: Total frequency offset between receiver and transmitter (Hz) fDEV: Single-sided frequency deviation Baudrate: The baud rate given is bit/sec
Sallen-Key Filters
A6..A0 0000001 D7 `1' D6 `0' D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
Each channel includes a pre-amplifier and a prefilter, which is a three-pole Sallen-Key lowpass filter. It protects the following switched-capacitor filter from strong adjacent channel signals, and it also works as an anti-aliasing filter. The preamplifier has a gain of 22.23dB. The maximum output voltage swing is about 1.4Vpp for a 2.25V power supply. In addition, the IF amplifier also performs offset cancellation. Gain varies by less than 0.5dB over a 2.0 - 2.5V variation in power supply. The third order Sallen-Key lowpass filter is programmable to four different cut-off frequencies according to the table below:
PF_FC1
0 0 1 1
RSSI
A6..A0 0000001 D7 `1' D6 `0' D5 `0' D4 `0' D3 RSSI_en D2 LD_en D1 PF_FC1 D0 PF_FC0
PF_FC0
0 1 0 1
Cut-off Freq. (kHz)
100 150 230 340
2,5 2 1,5 1
RSSI
Switched Capacitor Filter
A6..A0 0001000 D7 `1' D6 `1' D5 ScClk5 D4 ScClk4 D3 ScClk3 D2 ScClk2 D1 ScClk1 D0 ScClk0
0,5 0 -110 -100 -90 -80 Pin -70 (dBm) -60 -50 -40
The main channel filter is a switched-capacitor implementation of a six-pole elliptic low pass filter. The elliptic filter minimized the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the switched-capacitor filter is adjustable by changing the clock frequency. The clock frequency is designed to be 20 times the cut-off frequency. The clock frequency is derived from the reference crystal oscillator. A programmable 6-bit divider divides the frequency of the crystal oscillator. The cut-off frequency of the filter is given by:
Figure 9. RSSI Voltage
A Typical plot of the RSSI voltage as function of input power is shown in Figure 9. The RSSI has a dynamic range of about 50dB from about -110dBm to -60dBm input power. The RSSI can be used as a signal presence indicator. When a RF signal is received, the RSSI output increases. This could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life.
fCUT =
fXCO 40 ScClk
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Another application for which the RSSI could be used is to determine if transmit power can be reduced in a system. If the RSSI detects a strong signal, it could tell the transmitter to reduce the transmit power to reduce current consumption.
FEE
A6..A0 0010101 0010110 D7 FEE_7 D6 FEE_6 D5 FEE_5 D4 FEE_4 D3 FEEC_3 FEE_3 D2 FEEC_2 FEE_2 D1 FEEC_1 FEE_1 D0 FEEC_0 FEE_0
The result of the measurement is the FEE value, this can be read from register with address 0010110b. Negative values are stored as a binary no between 0000000 and 1111111. To calculate the negative value, a two's complement of this value must be performed. Only FEE modes where DN-pulses are counted (10 and 11) will give a negative value. When the FEE value has been read, the frequency offset can be calculated as follows: Mode UP: Mode DN: Foffset = R/(2P)x(FEE-Fp) Foffset = R/(2P)x(FEE+Fp)
The Frequency Error Estimator (FEE) uses information from the demodulator to calculate the frequency offset between the receive frequency and the transmitter frequency. The output of the FEE can be used to tune the XCO frequency, both for production calibration and for compensation for crystal temperature drift and aging. The input to the FEE circuit are the up and down pulses from the demodulator. Every time a `1' is updated, an UPpulse is coming out of the demodulator and the same with the DN-pulse every time the `0' is updated. The expected no. of pulses for every received symbol is 2 times the modulation index (). The FEE can operate in three different modes; counting only UP-pulses, only DN-pulses or counting UP+DN pulses. The no. of received symbols to be counted is either 8, 16, 32 or 64. This is set by the FEEC_0...FEEC_3 control bit, as follows:
FEEC_1 0 0 1 1 FEEC_0 0 1 0 1 FEE Mode Off Counting UP pulses Counting DN pulses Counting UP and DN pulses. UP increments the counter, DN decrements it. No. of symbols used for the measurement 8 16 32 65
Mode UP+DN: Foffset = R/(4P)x(FEE) where FEE is the value stored in the FEE register, (Fp is the single sided frequency deviation, P is the no. of symbols/data bit counted and R is the symbol/data rate. A positive Foffset means that the received signal has a higher frequency than the receiver frequency. To compensate for this, the receivers XCO frequency should be increased. It is recommended to use Mode UP+DN for two reasons, you do not need to know the actual frequency deviation and this mode gives the best accuracy.
FEEC_3 0 0 1 1
FEEC_2 0 1 0 1
Table 8. FEEC Control Bit
Bit Synchronizer
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0 0000110 `0' `0' `0' BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2 0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
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A bit synchronizer can be enabled in receive mode by selecting the synchronous mode (Sync_en=1). The DataClk pin will output a clock with twice the frequency of the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20 kHz). A received symbol/bit on DataIXO will be output on rising edge of DataClk. The micro controller should therefore, sample the symbol/bit on falling edge of DataClk. The bit synchronizer uses a clock that needs to be programmed according to the bit rate. The clock frequency should be 16 times the actual bit rate (a bit rate of 20 kbit/sec needs a bit synchronizer clock with frequency of 320 kHz). The clock frequency is set by the following formula: fBITSYNC_CLK = where fBITSYNC_CLK: The bit synchronizer clock frequency (16 times higher than the bit rate) fXCO: Crystal oscillator frequency Refclk_K: 6 bit divider, values between 1 and 63 BitSync_clkS: Bit synchronizer setting, values between 0 and 7 Refclk_K is also used to derive the modulator clock and the bit rate clock. At the beginning of a received data package, the bit synchronizer clock frequency is not synchronized to the bit rate. When these two are maximum offset to each other, it takes 22 bit/symbols before synchronization is achieved. fXCO Refclk_K x 2 (7-BITSYNC_clkS)
and A values is given in chapter Frequency synthesizer. The divider values stored in the M0-, N0-, and A0registers will be used when transmitting a `0' and the M1-, N1-, and A1-registers will be used to transmit a `1'. The difference between the two carrier frequencies corresponds to the double-sided frequency deviation. The data to be transmitted shall be applied to pin DataIXO (see chapter Transceiver sync-/non-synchronous mode on how to use the pin DataClk). The DataIXO pin is set as input in transmit mode and output in receive mode.
Using the XCO-tune Bits
The module has a built-in mechanism for tuning the frequency of the crystal oscillator and is often used in combination with the Frequency Error Estimator (FEE). The XCO tuning is designed to eliminate or reduce initial frequency tolerance of the crystal and/or the frequency stability over temperature. A procedure for using the XCO tuning feature in combination with the FEE is given below. The MICRF600 measures the frequency offset between the receivers LO frequency and the frequency of the transmitter. The receiver XCO frequency can be tuned until the receiver and transmitter frequencies are equal. A procedure like this can be called during production (storing the calibrated XCO_tune value), at regular intervals or implemented in the communication protocol when the frequency has changed. The MICRF600 development system can test this feature. Example: In FEE, count up+down pulses, counting 8 bits: A perfect case ==> FEE = 0 If FEE > 0: LO is too low, increase LO by decreasing XCO_tune value v.v. for FEE < 0 FEE field holds a number in the range -128, ... , 127. However, it keeps counting above/below the range, which is: If FEE = -128 and still counting dwn-pulses: 1) =>-129 = +127 2) 126 3) 125 To avoid this situation, always make sure max count is between limits.
Transmitter
Power Amplifier
A6..A0 0000000 0000001 D7 LNA_by `1' D6 PA2 `0' D5 PA1 `0' D4 PA0 `0' D3 Sync_en RSSI_en D2 Mode1 LD_en D1 Mode0 PF_FC1 D0 '1' PF_FC0
The maximum output power is approximately 10dBm for a 50 load. The output power is programmable in seven steps, with approximately 3dB between each step. Bits PA2 - PA0, control this. PA2 - PA0 = 1 give the maximum output power. The power amplifier can be turned off by setting PA2 - PA0 = 0. For all other combinations the PA is on and has maximum power when PA2 - PA0 = 1.
Frequency Modulation
FSK modulation is applied by switching between two sets of dividers (M,N,A). The formula for calculating the M, N September 2005
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Application Circuit Illustration
Assembling the MICRF600
Recommended Reflow Temperature Profile When the MICRF600 module is being automatically assembled to a PCB, care must be taken not to expose the module for temperature above the maximum specified. Figure 12 shows the recommended reflow temperature profile.
LDO MCU MICRF600 4004
Figure 10. Circuit illustration of MICRF600, LDO and MCU
Figure 10 shows a typical set-up with the MICRF600, a Low-Drop-Out voltage regulator (LDO) and a microcontroller (MCU). When the MICRF600 and the MCU runs on the same power supply (min 2.0, max. 2.5V), the IO can be connected directly to the MCU. If the MCU needs a higher VDD than the maximum specified VDD of the MICRF600 (2.5V), voltage dividers need to be added on the IO lines not to override the max. input voltage. Figure 11 shows a recommended voltage divider circuit for a MCU running at 3.0V and the MICRF600 at 2.5V.
MICRF6xx 3k3 CS CS MCU
Figure 12. Recommended Reflow Temperature Reflow
18k 3k3 SCLK SCLK
Shock/Vibration during Reflow The module has several components inside which are assembled in a reflow process. These components may reflow again when the module is assembled onto a PCB. It is therefore, important that the module is not subjected to any mechanical shock or vibration during this process. Handassembling the MICRF600 It is recommended that solder paste also be used during hand assembling of the module. Because of the module ground pad on the bottom side, the module will be assembled most efficiently if the heat is being subjected to the bottom side of the PCB. The heat will be transferred trough the PCB due the ground vias under the module (see Layout Considerations). In addition, it is recommended that a solder tip be used on the signal and power pads. This will ensure that the solder points are properly melted.
18k 3k3 IO IO
18k 15k DATAIXO DATACLK LD RSSI DATAIXO DATACLK LD RSSI
Figure 11. How to connect MCU600 (2.5V) and MCU (3.0V)
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Layout
Recommended Land Pattern Figure 12 shows a recommended land pattern that facilitates both automatic and hand assembling.
Layout Considerations Except for the antenna input/output signal, only digital and low frequency signals need to interface with the module. There is therefore no need of years of RF expertise to do a successful layout, as long as the following few points are being followed:
* Proper ground is needed. If the PCB is 2-layer, the bottom layer should be kept only for ground. Avoid signal traces that split the ground plane. For a 4layer PCB, it is recommended the second layer only for ground be kept. A ground via should be placed close to all the ground pins. The bottom ground pad should be penetrated with 4-16 ground vias. The antenna has a impedance of ~50. The antenna trace should be kept to 50 to avoid signal reflection and loss of performance. Any transmission line calculator can be used to find the needed trace width given a board build up. Example: A trace width of 44 mil (1.12 mm) gives 50 impedance on a FR4 board (dielectric cons=4.4) with copper thickness of 35m and height (layer 1-layer 2 spacing) of 0.61 mm.
*
*
Figure 13. Recommended Land Pattern
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Package Dimensions
3 4 5 6 7 8
11.5 0.05mm 0.71 0.02mm
16
15
13
14
12
11
10
xxxx
3.0 0.2mm
14.1 0.1mm 13.22mm
Figure 14. Package Dimensions
Tape Dimensions
Figure 15. Tape Dimensions
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
(c) 2005 Micrel, Incorporated.
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